As Moore's Law has been predicted, the capacity of memory cells on silicon for the past 15-20 years has effectively doubled each year. Moore's Law roughly states that every year the amount of devices such as transistor gates or memory cells on a silicon wafer will double, thus doubling the capacity of the typical chip while the price will essentially stay the same. As the devices continue to shrink, device technology is starting to reach a barrier known as the quantum limit, that is, they are actually approaching atomic dimensions, so the cells cannot get any smaller.
As a response to the limitations of directly shrinking transistor gates and memory cells, the “More than Moore's Law” movement has taken hold to push beyond simply shrinking cell size to increase the chip functionality. The focus is directed instead on methods to improve system integration as the means to increase the functionality and decrease the size of the final electronics product. For example, system-on-package methods combine individual chips with different functionalities such as microprocessor, microcontroller, sensor, memory, and others in one package rather than connecting them over a printed-circuit board with large discreet passive components. The system-on-package method further addresses sizes of discreet passive components—such as resistors, capacitors, inductors, antennas, filters, and switches by using micrometer-scale thin-film versions of discrete components. Another example is system-on-chip, which seeks to build entire signal-processing systems or subsystems with diverse functions on a chip of silicon—a system-on-chip, or SOC. Such a chip may include digital logic and memory for computation, analog and RF communications circuitry, and other circuit functions. Usually, these dissimilar circuits not only operate at different voltages but also require different processing steps during manufacture. Such differences have traditionally been a barrier to integrating such diverse circuitry on a single chip. For example, the processes for manufacturing microprocessors and flash nonvolatile memory chips are so different that the cost of manufacturing the two types of devices on the same chips is the same or more as the cost of manufacturing the two chips separately. Thus a different type of memory device while can be more easily and economically integrated with digital logic, analog, and RF circuitry is needed.
Separately, disk drives have been a type of information storage which provided a significant portion peak capacity. The storage density provided by disk drives have been cheaper than semiconductor memory devices at least partially due to the way disk drives store and read individual bits of information in individual domains (magnetic transition sites) with an external probe. This method of storing and reading the information does not require individual circuit connections for each bit of storage location, thus requiring significantly less overhead than storage in semiconductor memory which does require the individual circuit connections. The individually connected semiconductor memory such as Flash memory, however, is preferable to disk drives in terms of resistance to shock as it has no moving parts which may be damaged by movement and shock.
As semiconductor device scaling passes 90 nanometer feature size, or node to 45 and 25 nanometer nodes, the semiconductor memory density are beginning to reach similar density and cost as disk drive storage. Multiple bit storage per device, where a multiple of data bits may be stored in a single cell by a division of ranges, has also been employed to increase density and reduce cost.
Semiconductor memories such as flash memory of the floating gate or charge trapping types suffer from other issues due to scaling. As the size of the devices become smaller, variations of a few electrons begin to manifest as large variations in device characteristics such as current, write speed, and erase speed. Such large variations further require increased write, read, and erase time to reach the same distribution ranges for operation and reduce the supportable dynamic ranges for multiple bit storage.
Yet one more concern for traditional flash type of semiconductor memory scaling is the reduction of the number of write/erase cycle the cell will tolerate before it permanently fails. Prior to the substantial reduction in cell size, the typical flash memory write/erase cycle tolerance rating is in the range of 1,000,000, however, as the feature size reduces in size, write/erase cycle tolerance rating has diminished to the range of 3,000 cycles. This reduction of write/erase cycle tolerance limits the applications for the memory. For example, for a memory device to also function in current SRAM and DRAM applications, such memory must tolerate data exchange at much higher repetition rates, typically several times per microsecond, resulting in 1,000,000 or more cycles.
Accordingly, what is desired are a memory device, system and method which overcome the above-identified problems. The memory device, system and method should be easily implemented, cost effective and adaptable to existing storage applications. The system and method should also be simple to integrate with other ICs in terms of processing and operating voltages. The present disclosure addresses such a need.